refactor: modifiers aren't an enum.
This commit is contained in:
Jackson Netherwood-Imig
+145
-177
@@ -1,5 +1,4 @@
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/// Corresponds to DRM_FORMAT_* in `<drm/drm_fourcc.h>`
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pub const DrmFormat = enum(u32) {
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pub const Format = enum(u32) {
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pub const big_endian: u32 = 1 << 31;
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invalid = 0,
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@@ -131,150 +130,35 @@ pub const DrmFormat = enum(u32) {
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yvu444 = fourccCode('Y', 'V', '2', '4'),
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_, // Some formats involved with dmabuf aren't defined here
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fn fourccCode(a: u8, b: u8, c: u8, d: u8) u32 {
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return @as(u32, a) | (@as(u32, b) << 8) | (@as(u32, c) << 16) | (@as(u32, d) << 24);
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}
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};
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/// Contains most DRM_FORMAT_MOD* definitions from `<drm/drm_fourcc.h>`
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pub const DrmFormatMod = enum(u64) {
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pub const generic_16_16_tile: DrmFormatMod = .samsung_16_16_tile;
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pub const FormatModifiers = packed struct(u64) {
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raw: u56,
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vendor: Vendor,
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pub const vivante_ts_64_4: u64 = 1 << 48;
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pub const vivante_ts_64_2: u64 = 2 << 48;
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pub const vivante_ts_128_4: u64 = 3 << 48;
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pub const vivante_ts_256_4: u64 = 4 << 48;
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pub const vivante_ts_mask: u64 = 0xf << 48;
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pub const vivante_comp_dec400: u64 = 1 << 52;
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pub const vivante_comp_mask: u64 = 0xf << 52;
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pub const vivante_ext_mask = vivante_ts_mask | vivante_comp_mask;
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pub fn resolve(self: FormatModifiers) Resolved {
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return switch (self.vendor) {
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.none => .{ .none = .resolve(self.raw) },
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.intel => .{ .intel = self.raw }, // TODO
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.amd => .{ .amd = self.raw }, // TODO
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.nvidia => .{ .nvidia = .resolve(self.raw) },
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.samsung => .{ .samsung = self.raw }, // TODO
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.qualcomm => .{ .qualcomm = self.raw }, // TODO
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.vivante => .{ .vivante = self.raw }, // TODO
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.broadcom => .{ .broadcom = self.raw }, // TODO
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.arm => .{ .arm = self.raw }, // TODO
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.allwinner => .{ .allwinner = self.raw }, // TODO
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.amlogic => .{ .amlogic = self.raw }, // TODO
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.mtk => .{ .mtk = self.raw }, // TODO
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.apple => .{ .apple = self.raw }, // TODO
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};
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}
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pub const afbc_block_size_mask: u4 = 0xf;
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pub const afbc_block_size_16x16: u64 = 1;
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pub const afbc_block_size_32x8: u64 = 2;
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pub const afbc_block_size_64x4: u64 = 3;
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pub const afbc_block_size_32x8_64x4: u64 = 4;
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pub const afbc_ytr: u64 = 1 << 4;
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pub const afbc_split: u64 = 1 << 5;
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pub const afbc_sparse: u64 = 1 << 6;
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pub const afbc_cbr: u64 = 1 << 7;
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pub const afbc_tiled: u64 = 1 << 8;
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pub const afbc_sc: u64 = 1 << 9;
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pub const afbc_db: u64 = 1 << 10;
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pub const afbc_bch: u64 = 1 << 11;
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pub const afbc_usm: u64 = 1 << 12;
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pub const afrc_cu_size_mask: u4 = 0xf;
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pub const afrc_cu_size_16: u64 = 1;
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pub const afrc_cu_size_24: u64 = 2;
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pub const afrc_cu_size_32: u64 = 3;
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pub const afrc_layout_scan: u64 = 1 << 8;
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pub const amlogic_fbc_layout_basic: u64 = 1;
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pub const amlogic_fbc_layout_scatter: u64 = 2;
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pub const amlogic_fbc_option_mem_saving: u64 = 1 << 0;
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pub const amd_tile_ver_gfx9 = 1;
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pub const amd_tile_ver_gfx10 = 2;
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pub const amd_tile_ver_gfx10_rbplus = 3;
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pub const amd_tile_ver_gfx11 = 4;
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pub const amd_tile_ver_gfx12 = 5;
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pub const amd_tile_gfx9_64k_s = 9;
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pub const amd_tile_gfx9_64k_d = 10;
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pub const amd_tile_gfx9_64k_s_x = 25;
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pub const amd_tile_gfx9_64k_d_x = 26;
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pub const amd_tile_gfx9_64k_r_x = 27;
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pub const amd_tile_gfx11_256k_r_x = 31;
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pub const amd_tile_gfx12_256b_2d = 1;
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pub const amd_tile_gfx12_4k_2d = 2;
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pub const amd_tile_gfx12_64k_2d = 3;
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pub const amd_tile_gfx12_256k_2d = 4;
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pub const amd_dcc_block_64b = 0;
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pub const amd_dcc_block_128b = 1;
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pub const amd_dcc_block_256b = 2;
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pub const amd_tile_version_shift = 0;
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pub const amd_tile_version_mask = 0xff;
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pub const amd_tile_shift = 8;
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pub const amd_tile_mask = 0x1f;
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pub const amd_dcc_shift = 13;
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pub const amd_dcc_mask = 0x1;
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pub const amd_dcc_retile_shift = 14;
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pub const amd_dcc_retile_mask = 0x1;
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pub const amd_dcc_pipe_align_shift = 15;
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pub const amd_dcc_pipe_align_mask = 0x1;
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pub const amd_dcc_independent_64b_shift = 16;
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pub const amd_dcc_independent_64b_mask = 0x1;
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pub const amd_dcc_independent_128b_shift = 17;
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pub const amd_dcc_independent_128b_mask = 0x1;
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pub const amd_dcc_max_compressed_block_shift = 18;
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pub const amd_dcc_max_compressed_block_mask = 0x3;
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pub const amd_dcc_constant_encode_shift = 20;
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pub const amd_dcc_constant_encode_mask = 0x1;
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pub const amd_pipe_xor_bits_shift = 21;
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pub const amd_pipe_xor_bits_mask = 0x7;
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pub const amd_bank_xor_bits_shift = 24;
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pub const amd_bank_xor_bits_mask = 0x7;
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pub const amd_packers_shift = 27;
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pub const amd_packers_mask = 0x7;
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pub const amd_rb_shift = 30;
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pub const amd_rb_mask = 0x7;
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pub const amd_pipe_shift = 33;
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pub const amd_pipe_mask = 0x7;
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invalid = 0x00ffffffffffffff,
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linear = fourccModCode(.none, 0),
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intel_x_tiled = fourccModCode(.intel, 1),
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intel_y_tiled = fourccModCode(.intel, 2),
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intel_yf_tiled = fourccModCode(.intel, 3),
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intel_y_tiled_ccs = fourccModCode(.intel, 4),
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intel_yf_tiled_ccs = fourccModCode(.intel, 5),
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intel_y_tiled_gen12_rc_css = fourccModCode(.intel, 6),
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intel_y_tiled_gen12_mc_css = fourccModCode(.intel, 7),
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intel_y_tiled_gen12_rc_css_cc = fourccModCode(.intel, 8),
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intel_4_tiled = fourccModCode(.intel, 9),
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intel_4_tiled_dg2_rc_ccs = fourccModCode(.intel, 10),
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intel_4_tiled_dg2_mc_ccs = fourccModCode(.intel, 11),
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intel_4_tiled_dg2_rc_ccs_cc = fourccModCode(.intel, 12),
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intel_4_tiled_mtl_rc_ccs = fourccModCode(.intel, 13),
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intel_4_tiled_mtl_mc_ccs = fourccModCode(.intel, 14),
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intel_4_tiled_mtl_rc_ccs_cc = fourccModCode(.intel, 15),
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intel_4_tiled_lnl_ccs = fourccModCode(.intel, 16),
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intel_4_tiled_bmg_ccs = fourccModCode(.intel, 17),
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samsung_64_32_tile = fourccModCode(.samsung, 1),
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samsung_16_16_tile = fourccModCode(.samsung, 2),
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qualcomm_compressed = fourccModCode(.qualcomm, 1),
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qualcomm_tiled2 = fourccModCode(.qualcomm, 2),
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qualcomm_tiled3 = fourccModCode(.qualcomm, 3),
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vivante_tiled = fourccModCode(.vivante, 1),
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vivante_super_tiled = fourccModCode(.vivante, 2),
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vivante_split_tiled = fourccModCode(.vivante, 3),
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vivante_split_super_tiled = fourccModCode(.vivante, 4),
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nvidia_tegra_tiled = fourccModCode(.nvidia, 1),
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nvidia_16bx2_block_1_gob = nvidia16Bx2Block(0),
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nvidia_16bx2_block_2_gob = nvidia16Bx2Block(1),
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nvidia_16bx2_block_4_gob = nvidia16Bx2Block(2),
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nvidia_16bx2_block_8_gob = nvidia16Bx2Block(3),
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nvidia_16bx2_block_16_gob = nvidia16Bx2Block(4),
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nvidia_16bx2_block_32_gob = nvidia16Bx2Block(5),
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broadcom_vc4_t_tiled = fourccModCode(.broadcom, 1),
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broadcom_sand32 = fourccModCode(.broadcom, 2),
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broadcom_sand64 = fourccModCode(.broadcom, 3),
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broadcom_sand128 = fourccModCode(.broadcom, 4),
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broadcom_sand256 = fourccModCode(.broadcom, 5),
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broadcom_uif = fourccModCode(.broadcom, 6),
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arm_16x16_block_u_interleaved = armModCode(.misc, 1),
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allwinner_tiled = fourccModCode(.allwinner, 1),
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_, // This enum definately isn't complete so we'll leave it non-exhaustive for now
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};
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const Vendor = enum(u8) {
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pub const Vendor = enum(u8) {
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none = 0,
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intel = 0x01,
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amd = 0x02,
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@@ -288,39 +172,123 @@ const Vendor = enum(u8) {
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amlogic = 0x0a,
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mtk = 0x0b,
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apple = 0x0c,
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};
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pub const Resolved = union(Vendor) {
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none: None,
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intel: u56,
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amd: u56,
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nvidia: Nvidia,
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samsung: u56,
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qualcomm: u56,
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vivante: u56,
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broadcom: u56,
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arm: u56,
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allwinner: u56,
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amlogic: u56,
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mtk: u56,
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apple: u56,
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};
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pub const None = union(enum) {
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invalid: void,
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unknown: u56,
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pub fn resolve(raw: u56) None {
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return switch (raw) {
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0xffffffffffffff => .invalid,
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else => |val| .{ .unknown = val },
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};
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}
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};
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pub const Nvidia = union(enum) {
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tegra_tiled: void,
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block_linear_16bx2_1_gob: void,
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block_linear_16bx2_2_gob: void,
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block_linear_16bx2_4_gob: void,
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block_linear_16bx2_8_gob: void,
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block_linear_16bx2_16_gob: void,
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block_linear_16bx2_32_gob: void,
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block_linear_2d: BlockLinear2D,
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pub fn resolve(raw: u56) Nvidia {
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return switch (raw) {
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1 => .tegra_tiled,
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bl2dCode(0) => .block_linear_16bx2_1_gob,
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bl2dCode(1) => .block_linear_16bx2_2_gob,
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bl2dCode(2) => .block_linear_16bx2_4_gob,
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bl2dCode(3) => .block_linear_16bx2_8_gob,
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bl2dCode(4) => .block_linear_16bx2_16_gob,
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bl2dCode(5) => .block_linear_16bx2_32_gob,
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else => |val| .{ .block_linear_2d = .fromRaw(val) },
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};
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}
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pub const BlockLinear2D = struct {
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height: u16,
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page_kind: u8,
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gob_height: GobHeight,
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page_kind_generation: PageKindGeneration,
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sector_layout: SectorLayout,
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compression_type: CompressionType,
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fn fromRaw(raw: u56) BlockLinear2D {
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const h: u4 = @intCast(raw & 0xf);
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const k: u8 = @intCast((raw >> 12) & 0xff);
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const g: u2 = @intCast((raw >> 20) & 0x3);
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const s: u1 = @intCast((raw >> 22) & 0x1);
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const c: u3 = @intCast((raw >> 23) & 0x7);
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const height: u16 = @as(u16, 1) << h;
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const page_kind: u8 = k;
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const gob_height: GobHeight = switch (g) {
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1 => .@"4",
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0, 2 => .@"8",
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else => unreachable,
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};
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const page_kind_generation: PageKindGeneration = @enumFromInt(g);
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const sector_layout: SectorLayout = @enumFromInt(s);
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const compression_type: CompressionType = @enumFromInt(c);
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return BlockLinear2D{
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.height = height,
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.page_kind = page_kind,
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.gob_height = gob_height,
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.page_kind_generation = page_kind_generation,
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.sector_layout = sector_layout,
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.compression_type = compression_type,
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};
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}
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pub const GobHeight = enum {
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@"4",
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@"8",
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reserved,
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};
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pub const PageKindGeneration = enum {
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@"Fermi - Volta, Tegra K1+",
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@"G80 - GT2XX",
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@"Turing+",
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};
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pub const SectorLayout = enum {
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@"Tegra K1 - Tegra Parker/TX2",
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@"Desktop GPU and Tegra Xavier+",
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};
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pub const CompressionType = enum {
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none,
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@"ROP/3D, layout 1",
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@"ROP/3D, layout 2",
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@"CDE horizontal",
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@"CDE vertical",
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};
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};
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fn bl2dCode(h: u4) u56 {
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return @as(u56, h) | 0x10;
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}
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};
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};
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fn fourccCode(a: u8, b: u8, c: u8, d: u8) u32 {
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return @as(u32, a) | (@as(u32, b) << 8) | (@as(u32, c) << 16) | (@as(u32, d) << 24);
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}
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fn fourccModCode(vendor: Vendor, value: u56) u64 {
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return (@as(u64, @intFromEnum(vendor)) << 56) | (value & 0x00ffffffffffffff);
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}
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fn nvidiaBlockLinear2d(c: u3, s: u1, g: u2, k: u8, h: u4) u64 {
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return fourccModCode(.nvidia, @as(u56, 0x10) |
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@as(u56, h & 0xf) |
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(@as(u56, k & 0xff) << 12) |
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(@as(u56, g & 0x3) << 20) |
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(@as(u56, s & 0x1) << 22) |
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(@as(u56, c) & 0x7) << 23);
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}
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fn nvidia16Bx2Block(v: u4) u64 {
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return nvidiaBlockLinear2d(0, 0, 0, 0, v);
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}
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const ArmModType = enum(u4) {
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afbc = 0,
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misc = 1,
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afrc = 2,
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};
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fn armModCode(_type: ArmModType, val: u52) u64 {
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return fourccModCode(.arm, (@as(u64, @intFromEnum(_type)) << 52) | (val & 0x000fffffffffffff));
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}
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test {
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@import("std").testing.refAllDecls(@This());
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}
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